1. Field of the Invention
The present invention relates generally to a semiconductor device capable of adjusting the threshold voltage for optimal device operations, and more particularly to a semiconductor device capable of threshold voltage adjustment by applying an external voltage and a method for manufacturing the same by which a partial SOI structure is realized.
2. Description of the Prior Art
As generally known, a MOSFET in a semiconductor device operates sensitively in response to a threshold voltage (Vt). In order to obtain an optimal threshold voltage value of the MOSFET, issues relating to optimization of impurity implantation and/or thermal processes, and the like, are becoming important issues in the field of semiconductor manufacturing processes.
As semiconductor devices are miniaturized due to high-integration, more excessive impurity implantation is conventionally required in order to adjust the threshold voltage to an appropriate value. This excessive impurity implantation for purposes of adjusting the threshold voltage inevitably leads to deterioration of the device refresh characteristics and lowering of the device reliability due to the undesired dopant diffusion. Consequently, the conventional technique of excessively implanting impurity to adjust the threshold voltage does not lead to satisfactory results, especially for a highly integrated device.
Another conventional method applies a back bias to the body of a device for purposes of adjusting the threshold voltage. However, this conventional technique too has limitations, because the back bias will have less and less influence on the body as the semiconductor device size becomes small. In particular, since the channel and the body regions are surrounded by gates in a multiple gate structure (such as a double gate, a triple gate, or a surrounding gate structure) the back bias will have no influence on the body. The result is that it is impossible to adjust the threshold voltage by applying the back bias.
In conclusion, it is difficult to obtain an optimal threshold voltage in a highly integrated semiconductor device by applying the conventional techniques of the impurity implantation or thermal or other conventional processes. This presents challenges to securing optimal device characteristics coincident with the high integration of the semiconductor devices.